Initial commit
This commit is contained in:
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[00:36:26] INFO Wrote I2C tree to /home/martin/proj/DFPlayerMB/build/builds/default/default.i2c_tree.md
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[00:36:26] INFO Wrote I2C tree to /home/martin/proj/DFPlayerMB/build/builds/default/default.i2c_tree.md
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[00:36:21] DEBUG Assignment: r1.resistance [r1.resistance] := [100Ω ± 10.00%]
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DEBUG Constraining r1.resistance to [100Ω ± 10.00%]
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[00:36:21] INFO Loading KiCad PCB file: /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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[00:36:21] INFO Loading KiCad PCB file: /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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[00:36:26] INFO Found 1 components with footprints
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DEBUG node_fps: {<r1|Resistor>: <r1|Resistor.footprint|KicadFootprint>}
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[00:36:26] INFO Found 1 components with footprints
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[00:36:21] INFO Picking 1 modules
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INFO Picking 1 modules in parallel
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DEBUG Iteration 0 |stages|=1, |graphs|=1, |V|=4----------------------------------------------
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DEBUG DONE Iteration 0 Phase 1.0: Canonical literal form G:1
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DEBUG DONE Iteration 0 Phase 1.2: Constrain within and domain G:3
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DEBUG DONE Iteration 0 Phase 1.3: Alias predicates to true G:3
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DEBUG Iteration 1 |stages|=5, |graphs|=3, |V|=11---------------------------------------------
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DEBUG DONE Iteration 1 Phase 1.24: Merge intersecting subsets G:3
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DEBUG DONE Iteration 1 Phase 1.25: Predicate flat terminate G:3
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DEBUG DONE Iteration 1 Phase 1.27: Predicate is!! True G:3
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DEBUG Iteration 2 |stages|=38, |graphs|=3, |V|=10--------------------------------------------
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[00:36:22] DEBUG POST https://components.atopileapi.com/v0/query
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{
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"queries": [
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{
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"package": null,
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"qty": 1,
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"endpoint": "resistors",
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"resistance": {
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"type": "Quantity_Interval_Disjoint",
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"data": {
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"intervals": {
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"type": "Numeric_Interval_Disjoint",
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"data": {
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"intervals": [
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{
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"type": "Numeric_Interval",
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"data": {
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"min": 90.0,
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"max": 110.0
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}
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}
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]
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}
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},
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"unit": "ohm"
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}
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},
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"max_power": null,
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"max_voltage": null
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}
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]
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}
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DEBUG Downloading API data C22775
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[00:36:24] DEBUG GET https://components.atopileapi.com/v0/component/lcsc/22775
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DEBUG Crawling datasheet for C22775
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[00:36:25] DEBUG Downloading model for C22775
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[00:36:26] DEBUG {
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0: {
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0: <r1|Resistor>
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}
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}
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INFO Picking 1 independent groups: {
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0: <r1|Resistor>
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}
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DEBUG Attached component C22775 to module r1:
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{'resistance': {'type': 'Quantity_Interval_Disjoint', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 99.00000002235174, 'max': 100.99999997764826}}]}}, 'unit': 'ohm'}}, 'max_power': {'type': 'Quantity_Set_Discrete', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 0.1, 'max': 0.1}}]}}, 'unit': 'watt'}},
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'max_voltage': {'type': 'Quantity_Set_Discrete', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 75.0, 'max': 75.0}}]}}, 'unit': 'volt'}}}
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--->
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max_power: r1.max_power
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max_voltage: r1.max_voltage
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resistance: r1.resistance
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INFO Slow-picked parts in 4.7s
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INFO Picked complete: picked 1 parts
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INFO Verify design
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DEBUG Iteration 0 |stages|=1, |graphs|=1, |V|=7----------------------------------------------
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DEBUG DONE Iteration 0 Phase 1.0: Canonical literal form G:1
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DEBUG DONE Iteration 0 Phase 1.2: Constrain within and domain G:3
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DEBUG DONE Iteration 0 Phase 1.3: Alias predicates to true G:3
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DEBUG Iteration 1 |stages|=5, |graphs|=3, |V|=17---------------------------------------------
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DEBUG DONE Iteration 1 Phase 1.24: Merge intersecting subsets G:3
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DEBUG DONE Iteration 1 Phase 1.25: Predicate flat terminate G:3
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DEBUG DONE Iteration 1 Phase 1.27: Predicate is!! True G:3
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DEBUG Iteration 2 |stages|=38, |graphs|=3, |V|=16--------------------------------------------
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[00:36:21] INFO Picking 1 modules
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INFO Picking 1 modules in parallel
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[00:36:26] INFO Picking 1 independent groups: {
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0: <r1|Resistor>
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}
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INFO Slow-picked parts in 4.7s
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INFO Picked complete: picked 1 parts
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INFO Verify design
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[00:36:21] INFO Running design checks for stage POST_DESIGN
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DEBUG Running post-design check `needs_erc_check` for `runtime_anon[9]`
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INFO Checking graph for ERC violations
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INFO Checking 0 Power
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INFO Checking for hv/lv shorts
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INFO Checking for power source shorts
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INFO Checking 0 explicit nets
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INFO Checking 1 passives
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[00:36:21] INFO Running design checks for stage POST_DESIGN
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INFO Checking graph for ERC violations
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INFO Checking 0 Power
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INFO Checking for hv/lv shorts
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INFO Checking for power source shorts
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INFO Checking 0 explicit nets
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INFO Checking 1 passives
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[00:36:26] INFO Running checks
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INFO Running design checks for stage POST_SOLVE
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DEBUG Running post-solve check `needs_erc_check` for `runtime_anon[9]`
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[00:36:26] INFO Running checks
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INFO Running design checks for stage POST_SOLVE
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[00:36:21] INFO Resolving bus parameters
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DEBUG [3m Timings [0m
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┏━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━┓
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┃[1m [0m[1mCategory [0m[1m [0m┃[1m [0m[1mValue[0m[1m [0m┃[1m [0m[1mUnit[0m[1m [0m┃
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┡━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━┩
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│[36m [0m[36mget parameter connections[0m[36m [0m│[32m [0m[32m28.92[0m[32m [0m│[33m [0m[33mµs [0m[33m [0m│
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│[36m [0m[36mmerge parameters [0m[36m [0m│[32m [0m[32m 9.24[0m[32m [0m│[33m [0m[33mµs [0m[33m [0m│
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└───────────────────────────┴───────┴──────┘
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[00:36:21] INFO Resolving bus parameters
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[00:36:26] INFO Adding `UNI_ROYAL_0603WAF1000T5E:R0603` as `r1` (R1)
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INFO Adding `LCSC`=`C22775` to `r1` (R1)
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INFO Adding `Manufacturer`=`UNI-ROYAL(Uniroyal Elec)` to `r1` (R1)
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INFO Adding `Partnumber`=`0603WAF1000T5E` to `r1` (R1)
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INFO Adding `PARAM_max_power`=`{"type": "Quantity_Set_Discrete", "data": {"intervals": {"type": "Numeric_Interval_Disjoint", "data": {"intervals": [{"type": "Numeric_Interval", "data": {"min": 0.1, "max": 0.1}}]}}, "unit": "watt"}}` to `r1` (R1)
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INFO Adding `PARAM_max_voltage`=`{"type": "Quantity_Set_Discrete", "data": {"intervals": {"type": "Numeric_Interval_Disjoint", "data": {"intervals": [{"type": "Numeric_Interval", "data": {"min": 75.0, "max": 75.0}}]}}, "unit": "volt"}}` to `r1` (R1)
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INFO Adding `PARAM_resistance`=`{"type": "Quantity_Interval_Disjoint", "data": {"intervals": {"type": "Numeric_Interval_Disjoint", "data": {"intervals": [{"type": "Numeric_Interval", "data": {"min": 99.00000002235174, "max": 100.99999997764826}}]}}, "unit": "ohm"}}` to `r1` (R1)
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INFO Adding `Datasheet`=`https://www.lcsc.com/datasheet/lcsc_datasheet_2411221126_UNI-ROYAL-Uniroyal-Elec-0603WAF1000T5E_C22775.pdf` to `r1` (R1)
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INFO Updating `Reference`->`R1` on `r1` (R1)
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INFO Updating `Value`->`100Ω ±1% 100mW` on `r1` (R1)
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INFO Adding `atopile_address`=`r1` to `r1` (R1)
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INFO Adding net `footprint-net-0`
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INFO Adding net `footprint-net-1`
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INFO Positioning 0 footprints
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INFO Applying routes
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INFO Backing up layout to /home/martin/proj/DFPlayerMB/build/builds/default/default.20250926-003626.kicad_pcb
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INFO Updating layout /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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[00:36:26] INFO Adding `UNI_ROYAL_0603WAF1000T5E:R0603` as `r1` (R1)
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INFO Adding `LCSC`=`C22775` to `r1` (R1)
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INFO Adding `Manufacturer`=`UNI-ROYAL(Uniroyal Elec)` to `r1` (R1)
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INFO Adding `Partnumber`=`0603WAF1000T5E` to `r1` (R1)
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INFO Adding `PARAM_max_power`=`{"type": "Quantity_Set_Discrete", "data": {"intervals": {"type": "Numeric_Interval_Disjoint", "data": {"intervals": [{"type": "Numeric_Interval", "data": {"min": 0.1, "max": 0.1}}]}}, "unit": "watt"}}` to `r1` (R1)
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INFO Adding `PARAM_max_voltage`=`{"type": "Quantity_Set_Discrete", "data": {"intervals": {"type": "Numeric_Interval_Disjoint", "data": {"intervals": [{"type": "Numeric_Interval", "data": {"min": 75.0, "max": 75.0}}]}}, "unit": "volt"}}` to `r1` (R1)
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INFO Adding `PARAM_resistance`=`{"type": "Quantity_Interval_Disjoint", "data": {"intervals": {"type": "Numeric_Interval_Disjoint", "data": {"intervals": [{"type": "Numeric_Interval", "data": {"min": 99.00000002235174, "max": 100.99999997764826}}]}}, "unit": "ohm"}}` to `r1` (R1)
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INFO Adding `Datasheet`=`https://www.lcsc.com/datasheet/lcsc_datasheet_2411221126_UNI-ROYAL-Uniroyal-Elec-0603WAF1000T5E_C22775.pdf` to `r1` (R1)
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INFO Updating `Reference`->`R1` on `r1` (R1)
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INFO Updating `Value`->`100Ω ±1% 100mW` on `r1` (R1)
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INFO Adding `atopile_address`=`r1` to `r1` (R1)
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INFO Adding net `footprint-net-0`
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INFO Adding net `footprint-net-1`
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INFO Positioning 0 footprints
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INFO Applying routes
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INFO Backing up layout to /home/martin/proj/DFPlayerMB/build/builds/default/default.20250926-003626.kicad_pcb
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INFO Updating layout /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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[00:36:26] INFO Writing parameters to /home/martin/proj/DFPlayerMB/build/builds/default/default.variables.md
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@@ -0,0 +1 @@
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[00:36:26] INFO Writing parameters to /home/martin/proj/DFPlayerMB/build/builds/default/default.variables.md
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