Initial commit
This commit is contained in:
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[01:09:27] INFO Wrote I2C tree to /home/martin/proj/DFPlayerMB/build/builds/default/default.i2c_tree.md
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[01:09:27] INFO Wrote I2C tree to /home/martin/proj/DFPlayerMB/build/builds/default/default.i2c_tree.md
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[01:09:23] DEBUG Assignment: power_filter_cap.capacitance [power_filter_cap.capacitance] := [376µF, 564µF]
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DEBUG Constraining power_filter_cap.capacitance to [376µF, 564µF]
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DEBUG Assignment: power_filter_cap.voltage [power_filter_cap.voltage] := [10V]
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DEBUG Constraining power_filter_cap.voltage to [10V]
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DEBUG Assignment: rx_protection_resistor.resistance [rx_protection_resistor.resistance] := [1kΩ ± 5.00%]
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DEBUG Constraining rx_protection_resistor.resistance to [1kΩ ± 5.00%]
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DEBUG Assignment: stereo_out_jack.TIP [TIP] := [1]
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DEBUG Constraining stereo_out_jack.TIP to [1]
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DEBUG Assignment: stereo_out_jack.RING [RING] := [2]
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DEBUG Constraining stereo_out_jack.RING to [2]
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DEBUG Assignment: stereo_out_jack.SLEEVE [SLEEVE] := [3]
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DEBUG Constraining stereo_out_jack.SLEEVE to [3]
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[01:09:23] INFO Loading KiCad PCB file: /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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[01:09:23] INFO Loading KiCad PCB file: /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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[01:09:27] INFO Found 8 components with footprints
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DEBUG node_fps: {<speaker_connector|JST_PH_Vertical_2Pin>: <speaker_connector|JST_PH_Vertical_2Pin.footprint|KicadFootprint>, <uart_connector|JST_PH_Vertical_4Pin>: <uart_connector|JST_PH_Vertical_4Pin.footprint|KicadFootprint>, <df_header_left|PinSocket_1x8_SMD>: <df_header_left|PinSocket_1x8_SMD.footprint|KicadFootprint>, <stereo_out_jack|AudioJack3_5mm>: <stereo_out_jack|AudioJack3_5mm.footprint|KicadFootprint>, <df_header_right|PinSocket_1x8_SMD>:
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<df_header_right|PinSocket_1x8_SMD.footprint|KicadFootprint>, <power_protection_diode|hongjiacheng_M1_package>: <power_protection_diode|hongjiacheng_M1_package.footprint|KicadFootprint>, <power_filter_cap|Elec_Cap_6_3x5_4>: <power_filter_cap|Elec_Cap_6_3x5_4.footprint|KicadFootprint>, <rx_protection_resistor|Resistor>: <rx_protection_resistor|Resistor.footprint|KicadFootprint>}
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[01:09:27] INFO Found 8 components with footprints
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[01:09:23] INFO Picking 1 modules
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INFO Picking 1 modules in parallel
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DEBUG Iteration 0 |stages|=1, |graphs|=1, |V|=14-------------------------------------
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DEBUG DONE Iteration 0 Phase 1.0: Canonical literal form G:1
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DEBUG DONE Iteration 0 Phase 1.2: Constrain within and domain G:8
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DEBUG DONE Iteration 0 Phase 1.3: Alias predicates to true G:8
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DEBUG Iteration 1 |stages|=5, |graphs|=8, |V|=36-------------------------------------
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DEBUG DONE Iteration 1 Phase 1.22: Fold IsSubset G:8
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DEBUG DONE Iteration 1 Phase 1.24: Merge intersecting subsets G:8
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DEBUG DONE Iteration 1 Phase 1.25: Predicate flat terminate G:8
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DEBUG DONE Iteration 1 Phase 1.27: Predicate is!! True G:8
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DEBUG Iteration 2 |stages|=38, |graphs|=8, |V|=34------------------------------------
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[01:09:25] DEBUG POST https://components.atopileapi.com/v0/query
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{
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"queries": [
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{
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"package": null,
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"qty": 1,
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"endpoint": "resistors",
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"resistance": {
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"type": "Quantity_Interval_Disjoint",
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"data": {
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"intervals": {
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"type": "Numeric_Interval_Disjoint",
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"data": {
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"intervals": [
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{
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"type": "Numeric_Interval",
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"data": {
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"min": 950.0,
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"max": 1050.0
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}
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}
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]
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}
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},
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"unit": "kiloohm"
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}
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},
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"max_power": null,
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"max_voltage": null
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}
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]
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}
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DEBUG Downloading API data C11702
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[01:09:26] DEBUG GET https://components.atopileapi.com/v0/component/lcsc/11702
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DEBUG Crawling datasheet for C11702
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[01:09:27] DEBUG {
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0: {
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0: <rx_protection_resistor|Resistor>
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}
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}
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INFO Picking 1 independent groups: {
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0: <rx_protection_resistor|Resistor>
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}
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DEBUG Attached component C11702 to module rx_protection_resistor:
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{'resistance': {'type': 'Quantity_Interval_Disjoint', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 990.0000002235174, 'max': 1009.9999997764826}}]}}, 'unit': 'ohm'}}, 'max_power': {'type': 'Quantity_Set_Discrete', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 0.0625, 'max': 0.0625}}]}}, 'unit': 'watt'}},
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'max_voltage': {'type': 'Quantity_Set_Discrete', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 50.0, 'max': 50.0}}]}}, 'unit': 'volt'}}}
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--->
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max_power: rx_protection_resistor.max_power
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max_voltage: rx_protection_resistor.max_voltage
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resistance: rx_protection_resistor.resistance
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INFO Slow-picked parts in 3.58s
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INFO Picked complete: picked 1 parts
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INFO Verify design
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DEBUG Iteration 0 |stages|=1, |graphs|=1, |V|=17-------------------------------------
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DEBUG DONE Iteration 0 Phase 1.0: Canonical literal form G:1
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DEBUG DONE Iteration 0 Phase 1.2: Constrain within and domain G:8
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DEBUG DONE Iteration 0 Phase 1.3: Alias predicates to true G:8
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DEBUG Iteration 1 |stages|=5, |graphs|=8, |V|=42-------------------------------------
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DEBUG DONE Iteration 1 Phase 1.22: Fold IsSubset G:8
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DEBUG DONE Iteration 1 Phase 1.24: Merge intersecting subsets G:8
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DEBUG DONE Iteration 1 Phase 1.25: Predicate flat terminate G:8
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DEBUG DONE Iteration 1 Phase 1.27: Predicate is!! True G:8
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DEBUG Iteration 2 |stages|=38, |graphs|=8, |V|=40------------------------------------
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[01:09:23] INFO Picking 1 modules
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INFO Picking 1 modules in parallel
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[01:09:27] INFO Picking 1 independent groups: {
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0: <rx_protection_resistor|Resistor>
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}
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INFO Slow-picked parts in 3.58s
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INFO Picked complete: picked 1 parts
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INFO Verify design
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[01:09:23] INFO Running design checks for stage POST_DESIGN
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DEBUG Running post-design check `needs_erc_check` for `runtime_anon[9]`
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INFO Checking graph for ERC violations
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INFO Checking 0 Power
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INFO Checking for hv/lv shorts
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INFO Checking for power source shorts
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INFO Checking 0 explicit nets
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INFO Checking 1 passives
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[01:09:23] INFO Running design checks for stage POST_DESIGN
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INFO Checking graph for ERC violations
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INFO Checking 0 Power
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INFO Checking for hv/lv shorts
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INFO Checking for power source shorts
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INFO Checking 0 explicit nets
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INFO Checking 1 passives
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[01:09:27] INFO Running checks
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INFO Running design checks for stage POST_SOLVE
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DEBUG Running post-solve check `needs_erc_check` for `runtime_anon[9]`
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[01:09:27] INFO Running checks
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INFO Running design checks for stage POST_SOLVE
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[01:09:23] INFO Resolving bus parameters
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DEBUG [3m Timings [0m
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┏━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━┓
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┃[1m [0m[1mCategory [0m[1m [0m┃[1m [0m[1mValue[0m[1m [0m┃[1m [0m[1mUnit[0m[1m [0m┃
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┡━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━┩
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│[36m [0m[36mget parameter connections[0m[36m [0m│[32m [0m[32m 3.98[0m[32m [0m│[33m [0m[33mµs [0m[33m [0m│
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│[36m [0m[36mmerge parameters [0m[36m [0m│[32m [0m[32m 4.4[0m[32m [0m│[33m [0m[33mµs [0m[33m [0m│
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└───────────────────────────┴───────┴──────┘
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@@ -0,0 +1 @@
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[01:09:23] INFO Resolving bus parameters
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[01:09:27] INFO Positioning 0 footprints
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INFO Applying routes
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INFO Backing up layout to /home/martin/proj/DFPlayerMB/build/builds/default/default.20250927-010927.kicad_pcb
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INFO No changes to layout. Not writing /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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@@ -0,0 +1,4 @@
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[01:09:27] INFO Positioning 0 footprints
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INFO Applying routes
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INFO Backing up layout to /home/martin/proj/DFPlayerMB/build/builds/default/default.20250927-010927.kicad_pcb
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INFO No changes to layout. Not writing /home/martin/proj/DFPlayerMB/layout/default/default.kicad_pcb
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@@ -0,0 +1 @@
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[01:09:27] INFO Writing parameters to /home/martin/proj/DFPlayerMB/build/builds/default/default.variables.md
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@@ -0,0 +1 @@
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[01:09:27] INFO Writing parameters to /home/martin/proj/DFPlayerMB/build/builds/default/default.variables.md
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