[00:48:43] INFO Picking 1 modules INFO Picking 1 modules in parallel DEBUG Iteration 0 |stages|=1, |graphs|=1, |V|=4---------------------------------------------- DEBUG DONE Iteration 0 Phase 1.0: Canonical literal form G:1 DEBUG DONE Iteration 0 Phase 1.2: Constrain within and domain G:3 DEBUG DONE Iteration 0 Phase 1.3: Alias predicates to true G:3 DEBUG Iteration 1 |stages|=5, |graphs|=3, |V|=11--------------------------------------------- DEBUG DONE Iteration 1 Phase 1.24: Merge intersecting subsets G:3 DEBUG DONE Iteration 1 Phase 1.25: Predicate flat terminate G:3 DEBUG DONE Iteration 1 Phase 1.27: Predicate is!! True G:3 DEBUG Iteration 2 |stages|=38, |graphs|=3, |V|=10-------------------------------------------- [00:48:44] DEBUG POST https://components.atopileapi.com/v0/query { "queries": [ { "package": null, "qty": 1, "endpoint": "resistors", "resistance": { "type": "Quantity_Interval_Disjoint", "data": { "intervals": { "type": "Numeric_Interval_Disjoint", "data": { "intervals": [ { "type": "Numeric_Interval", "data": { "min": 900.0, "max": 1100.0 } } ] } }, "unit": "kiloohm" } }, "max_power": null, "max_voltage": null } ] } DEBUG Crawling datasheet for C11702 [00:48:45] DEBUG { 0: { 0: } } INFO Picking 1 independent groups: { 0: } DEBUG Attached component C11702 to module r1: {'resistance': {'type': 'Quantity_Interval_Disjoint', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 990.0000002235174, 'max': 1009.9999997764826}}]}}, 'unit': 'ohm'}}, 'max_power': {'type': 'Quantity_Set_Discrete', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 0.0625, 'max': 0.0625}}]}}, 'unit': 'watt'}}, 'max_voltage': {'type': 'Quantity_Set_Discrete', 'data': {'intervals': {'type': 'Numeric_Interval_Disjoint', 'data': {'intervals': [{'type': 'Numeric_Interval', 'data': {'min': 50.0, 'max': 50.0}}]}}, 'unit': 'volt'}}} ---> max_power: r1.max_power max_voltage: r1.max_voltage resistance: r1.resistance INFO Slow-picked parts in 1.71s INFO Picked complete: picked 1 parts INFO Verify design DEBUG Iteration 0 |stages|=1, |graphs|=1, |V|=7---------------------------------------------- DEBUG DONE Iteration 0 Phase 1.0: Canonical literal form G:1 DEBUG DONE Iteration 0 Phase 1.2: Constrain within and domain G:3 DEBUG DONE Iteration 0 Phase 1.3: Alias predicates to true G:3 DEBUG Iteration 1 |stages|=5, |graphs|=3, |V|=17--------------------------------------------- DEBUG DONE Iteration 1 Phase 1.24: Merge intersecting subsets G:3 DEBUG DONE Iteration 1 Phase 1.25: Predicate flat terminate G:3 DEBUG DONE Iteration 1 Phase 1.27: Predicate is!! True G:3 DEBUG Iteration 2 |stages|=38, |graphs|=3, |V|=16--------------------------------------------