715 lines
20 KiB
Plaintext
715 lines
20 KiB
Plaintext
---
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description: ato is a declarative DSL to design electronics (PCBs) with.
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globs: *.ato, ato.yaml
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alwaysApply: true
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---
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ato is a declarative DSL to design electronics (PCBs) with.
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It is part of the atopile project.
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Atopile is run by the vscode/cursor/windsurf extension.
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The CLI (which is invoked by the extension) actually builds the project.
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# Not available in ato
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- if statements
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- while loops
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- functions (calls or definitions)
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- classes
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- objects
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- exceptions
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- generators
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# Ato Syntax
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ato sytax is heavily inspired by Python, but fully declarative.
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ato thus has no procedural code, and no side effects.
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## Examples of syntax
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```ato
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#pragma text
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#pragma func("X")
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# enable for loop syntax feature:
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#pragma experiment("FOR_LOOP)
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# --- Imports ---
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# Standard import (newline terminated)
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import ModuleName
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# Import with multiple modules (newline terminated)
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import Module1, Module2.Submodule
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# Import from a specific file/source (newline terminated)
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from "path/to/source.ato" import SpecificModule
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# Multiple imports on one line (semicolon separated)
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import AnotherModule; from "another/source.ato" import AnotherSpecific
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# Deprecated import form (newline terminated)
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# TODO: remove when unsupported
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import DeprecatedModule from "other/source.ato"
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# --- Top-level Definitions and Statements ---
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pass
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pass;
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"docstring-like statement"
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"docstring-like statement";
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top_level_var = 123
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# Compound statement
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pass; another_var = 456; "another docstring"
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# Block definitions
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component MyComponent:
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# Simple statement inside block (newline terminated)
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pass
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# Multiple simple statements on one line (semicolon separated)
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pass; internal_flag = True
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module AnotherBaseModule:
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pin base_pin
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base_param = 10
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interface MyInterface:
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pin io
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module DemoModule from AnotherBaseModule:
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# --- Declarations ---
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pin p1 # Pin declaration with name
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pin 1 # Pin declaration with number
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pin "GND" # Pin declaration with string
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signal my_signal # Signal definition
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a_field: AnotherBaseModule # Field declaration with type hint
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# --- Assignments ---
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# Newline terminated:
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internal_variable = 123
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# Semicolon separated on one line:
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var_a = 1; var_b = "string"
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# Cumulative assignment (+=, -=) - Newline terminated
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value = 1
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value += 1; value -= 1
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# Set assignment (|=, &=) - Newline terminated
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flags |= 1; flags &= 2
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# --- Connections ---
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p1 ~ base_pin
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mif ~> bridge
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mif ~> bridge ~> bridge
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mif ~> bridge ~> bridge ~> mif
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bridge ~> mif
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mif <~ bridge
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mif <~ bridge <~ bridge
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mif <~ bridge <~ bridge <~ mif
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bridge <~ mif
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# Semicolon separated on one line:
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p_multi1 ~ my_signal; p_multi2 ~ sig_multi1
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# --- Retyping ---
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instance.x -> AnotherBaseModule
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# --- Instantiation ---
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instance = new MyComponent
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container = new MyComponent[10]
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templated_instance_a = new MyComponent
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templated_instance_b = new MyComponent<int_=1>
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templated_instance_c = new MyComponent<float_=2.5>
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templated_instance_d = new MyComponent<string_="hello">
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templated_instance_e = new MyComponent<int_=1, float_=2.5, string_="hello">
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templated_instance_f = new MyComponent<int_=1, float_=2.5, string_="hello", bool_=True>
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# Semicolon separated instantiations (via assignment):
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inst_a = new MyComponent; inst_b = new AnotherBaseModule
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# --- Traits ---
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trait trait_name
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trait trait_name<int_=1>
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trait trait_name<float_=2.5>
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trait trait_name<string_="hello">
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trait trait_name<bool_=True>
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trait trait_name::constructor
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trait trait_name::constructor<int_=1>
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# Semicolon separated on one line:
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trait TraitA; trait TraitB::constructor; trait TraitC<arg_=1>
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# --- Assertions ---
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assert x > 5V
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assert x < 10V
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assert 5V < x < 10V
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assert x >= 5V
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assert x <= 10V
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assert current within 1A +/- 10mA
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assert voltage within 1V +/- 10%
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assert resistance is 1kohm to 1.1kohm
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# Semicolon separated on one line:
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assert x is 1V; assert another_param is 2V
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# --- Loops ---
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for item in container:
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item ~ p1
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# For loop iterating over a slice
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for item in container[0:4]:
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pass
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item.value = 1; pass
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# For loop iterating over a list literal of field references
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for ref in [p1, x.1, x.GND]:
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pass
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# --- References and Indexing ---
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# Reference with array index assignment
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array_element = container[3]
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# --- Literals and Expressions ---
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# Integer
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int_val = 100
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neg_int_val = -50
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hex_val = 0xF1
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bin_val = 0b10
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oct_val = 0o10
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# Float
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float_val = 3.14
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# Physical quantities
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voltage: V = 5V
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resistance: ohm = 10kohm
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capacitance: F = 100nF
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# Bilateral tolerance
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tolerance_val = 1kohm +/- 10%
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tolerance_abs = 5V +/- 500mV
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tolerance_explicit_unit = 10A +/- 1A
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# Bounded quantity (range)
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voltage_range = 3V to 3.6V
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# Boolean
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is_enabled = True
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is_active = False
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# String
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message = "Hello inside module"
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# Arithmetic expressions
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sum_val = 1 + 2
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diff_val = 10 - 3ohm
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prod_val = 5 * 2mA
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div_val = 10V / 2kohm # Results in current
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power_val = 2**3
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complex_expr = (5 + 3) * 2 - 1
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flag_check = state | MASK_VALUE
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# Comparisons
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assert voltage within voltage_range
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assert length <= 5mm
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assert height >= 2mm
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# --- Multi-line variations ---
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pass; nested_var=1; another=2
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complex_assignment = (
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voltage + resistance
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* capacitance
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)
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```
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## G4 Grammar
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```g4
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parser grammar AtoParser;
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options {
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superClass = AtoParserBase;
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tokenVocab = AtoLexer;
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}
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file_input: (NEWLINE | stmt)* EOF;
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pragma_stmt: PRAGMA;
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stmt: simple_stmts | compound_stmt | pragma_stmt;
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simple_stmts:
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simple_stmt (SEMI_COLON simple_stmt)* SEMI_COLON? NEWLINE;
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simple_stmt:
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import_stmt
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| dep_import_stmt
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| assign_stmt
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| cum_assign_stmt
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| set_assign_stmt
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| connect_stmt
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| directed_connect_stmt
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| retype_stmt
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| pin_declaration
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| signaldef_stmt
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| assert_stmt
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| declaration_stmt
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| string_stmt
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| pass_stmt
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| trait_stmt;
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compound_stmt: blockdef | for_stmt;
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blockdef: blocktype name blockdef_super? COLON block;
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// TODO @v0.4 consider ()
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blockdef_super: FROM type_reference;
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// TODO @v0.4 consider removing component (or more explicit code-as-data)
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blocktype: (COMPONENT | MODULE | INTERFACE);
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block: simple_stmts | NEWLINE INDENT stmt+ DEDENT;
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// TODO: @v0.4 remove the deprecated import form
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dep_import_stmt: IMPORT type_reference FROM string;
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import_stmt: (FROM string)? IMPORT type_reference (
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COMMA type_reference
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)*;
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declaration_stmt: field_reference type_info;
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field_reference_or_declaration:
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field_reference
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| declaration_stmt;
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assign_stmt: field_reference_or_declaration '=' assignable;
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cum_assign_stmt:
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field_reference_or_declaration cum_operator cum_assignable;
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// TODO: consider sets cum operator
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set_assign_stmt:
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field_reference_or_declaration (OR_ASSIGN | AND_ASSIGN) cum_assignable;
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cum_operator: ADD_ASSIGN | SUB_ASSIGN;
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cum_assignable: literal_physical | arithmetic_expression;
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assignable:
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string
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| new_stmt
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| literal_physical
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| arithmetic_expression
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| boolean_;
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retype_stmt: field_reference ARROW type_reference;
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directed_connect_stmt
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: bridgeable ((SPERM | LSPERM) bridgeable)+; // only one type of SPERM per stmt allowed. both here for better error messages
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connect_stmt: mif WIRE mif;
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bridgeable: connectable;
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mif: connectable;
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connectable: field_reference | signaldef_stmt | pindef_stmt;
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signaldef_stmt: SIGNAL name;
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pindef_stmt: pin_stmt;
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pin_declaration: pin_stmt;
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pin_stmt: PIN (name | number_hint_natural | string);
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new_stmt: NEW type_reference ('[' new_count ']')? template?;
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new_count: number_hint_natural;
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string_stmt:
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string; // the unbound string is a statement used to add doc-strings
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pass_stmt:
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PASS; // the unbound string is a statement used to add doc-strings
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list_literal_of_field_references:
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'[' (field_reference (COMMA field_reference)* COMMA?)? ']';
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iterable_references:
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field_reference slice?
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| list_literal_of_field_references;
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for_stmt: FOR name IN iterable_references COLON block;
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assert_stmt: ASSERT comparison;
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trait_stmt
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: TRAIT type_reference (DOUBLE_COLON constructor)? template?; // TODO: move namespacing to type_reference
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constructor: name;
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template: '<' (template_arg (COMMA template_arg)* COMMA?)? '>';
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template_arg: name ASSIGN literal;
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// Comparison operators --------------------
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comparison: arithmetic_expression compare_op_pair+;
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compare_op_pair:
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lt_arithmetic_or
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| gt_arithmetic_or
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| lt_eq_arithmetic_or
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| gt_eq_arithmetic_or
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| in_arithmetic_or
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| is_arithmetic_or;
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lt_arithmetic_or: LESS_THAN arithmetic_expression;
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gt_arithmetic_or: GREATER_THAN arithmetic_expression;
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lt_eq_arithmetic_or: LT_EQ arithmetic_expression;
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gt_eq_arithmetic_or: GT_EQ arithmetic_expression;
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in_arithmetic_or: WITHIN arithmetic_expression;
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is_arithmetic_or: IS arithmetic_expression;
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// Arithmetic operators --------------------
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arithmetic_expression:
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arithmetic_expression (OR_OP | AND_OP) sum
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| sum;
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sum: sum (PLUS | MINUS) term | term;
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term: term (STAR | DIV) power | power;
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power: functional (POWER functional)?;
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functional: bound | name '(' bound+ ')';
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bound: atom;
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// Primary elements ----------------
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slice:
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'[' (slice_start? COLON slice_stop? (COLON slice_step?)?)? ']'
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// else [::step] wouldn't match
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| '[' ( DOUBLE_COLON slice_step?) ']';
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slice_start: number_hint_integer;
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slice_stop: number_hint_integer;
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slice_step: number_hint_integer;
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atom: field_reference | literal_physical | arithmetic_group;
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arithmetic_group: '(' arithmetic_expression ')';
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literal_physical:
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bound_quantity
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| bilateral_quantity
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| quantity;
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bound_quantity: quantity TO quantity;
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bilateral_quantity: quantity PLUS_OR_MINUS bilateral_tolerance;
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quantity: number name?;
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bilateral_tolerance: number_signless (PERCENT | name)?;
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key: number_hint_integer;
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array_index: '[' key ']';
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// backwards compatibility for A.1
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pin_reference_end: DOT number_hint_natural;
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field_reference_part: name array_index?;
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field_reference:
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field_reference_part (DOT field_reference_part)* pin_reference_end?;
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type_reference: name (DOT name)*;
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// TODO better unit
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unit: name;
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type_info: COLON unit;
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name: NAME;
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// Literals
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literal: string | boolean_ | number;
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string: STRING;
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boolean_: TRUE | FALSE;
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number_hint_natural: number_signless;
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number_hint_integer: number;
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number: (PLUS | MINUS)? number_signless;
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number_signless: NUMBER;
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```
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# Most used library modules/interfaces (api of them)
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```ato
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interface Electrical:
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pass
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interface ElectricPower:
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hv = new Electrical
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lv = new Electrical
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module Resistor:
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resistance: ohm
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max_power: W
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max_voltage: V
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unnamed = new Electrical[2]
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module Capacitor:
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capacitance: F
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max_voltage: V
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unnamed = new Electrical[2]
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interface I2C:
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scl = new ElectricLogic
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sda = new ElectricLogic
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frequency: Hz
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address: dimensionless
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interface ElectricLogic:
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line = new Electrical
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reference = new ElectricPower
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```
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For the rest use the atopile MCP server
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- `get_library_interfaces` to list interfaces
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- `get_library_modules` to list modules
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- `inspect_library_module_or_interface` to inspect the code
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# Ato language features
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## experimental features
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Enable with `#pragma experiment("BRIDGE_CONNECT")`
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BRIDGE_CONNECT: enables `p1 ~> resistor ~> p2` syntax
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FOR_LOOP: enables `for item in container: pass` syntax
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TRAITS: enables `trait trait_name` syntax
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MODULE_TEMPLATING: enables `new MyComponent<param=literal>` syntax
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## modules, interfaces, parameters, traits
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A block is either a module, interface or component.
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Components are just modules for code-as-data.
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Interfaces describe a connectable interface (e.g Electrical, ElectricPower, I2C, etc).
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A module is a block that can be instantiated.
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Think of it as the ato equivalent of a class.
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Parameters are variables for numbers and they work with constraints.
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E.g `resistance: ohm` is a parameter.
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Constrain with `assert resistance within 10kohm +/- 10%`.
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It's very important to use toleranced values for parameters.
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If you constrain a resistor.resistance to 10kohm there won't be a single part found because that's a tolerance of 0%.
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Traits mark a module to have some kind of functionality that can be used in other modules.
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E.g `trait has_designator_prefix` is the way to mark a module to have a specific designator prefix that will be used in the designator field in the footprint.
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## connecting
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You can only connect interfaces of the same type.
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`resistor0.unnamed[0] ~ resistor0.unnamed[0]` is the way to connect two resistors in series.
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If a module has the `can_bridge` trait you can use the sperm operator `~>` to bridge the module.
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`led.anode ~> resistor ~> power.hv` connects the anode in series with the resistor and then the resistor in series with the high voltage power supply.
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## for loop syntax
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`for item in container: pass` is the way to iterate over a container.
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# Ato CLI
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## How to run
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You run ato commands through the MCP tool.
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## Packages
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Packages can be found on the ato registry.
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To install a package you need to run `ato add <PACKAGE_NAME>`.
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e.g `ato install atopile/addressable-leds`
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And then can be imported with `from "atopile/addressable-leds/sk6805-ec20.ato" import SK6805_EC20_driver`.
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And used like this:
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```ato
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module MyModule:
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led = new SK6805_EC20_driver
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```
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## Footprints & Part picking
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Footprint selection is done through the part choice (`ato create part` auto-generates ato code for the part).
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The `pin` keyword is used to build footprint pinmaps so avoid using it outside of `component` blocks.
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Preferrably use `Electrical` interface for electrical interfaces.
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A lot of times it's actually `ElectricLogic` for things like GPIOs etc or `ElectricPower` for power supplies.
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Passive modules (Resistors, Capacitors) are picked automatically by the constraints on their parameters.
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To constrain the package do e.g `package = "0402"`.
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To explictly pick a part for a module use `lcsc = "<LCSC_PART_NUMBER>"`.
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# Creating a package
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Package generation process:
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Review structure of other pacakges.
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1. Create new Directory in 'packages/packages' with naming convention '<vendor>-<device>' eg 'adi-adau145x'
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2. create an ato.yaml file in the new directory with the following content:
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```yaml
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requires-atopile: '^0.9.0'
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paths:
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src: '.'
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layout: ./layouts
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builds:
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default:
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entry: <device>.ato:<device>_driver
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example:
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entry: <device>.ato:Example
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```
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3. Create part using tool call 'search_and_install_jlcpcb_part'
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4. Import the part into the <device>.ato file
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5. Read the datasheet for the device
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6. Find common interfaces in the part eg I2C, I2S, SPI, Power
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7. Create interfaces and connect them
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power interfaces:
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power*<name> = new ElectricPower
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power*<name>.required = True # If critical to the device
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assert power\*<name>.voltage within <minimum*operating_voltage>V to <maximum_operating_voltage>V
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power*<name>.vcc ~ <device>.<vcc pin>
|
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power\_<name>.gnd ~ <device>.<gnd pin>
|
||
|
||
i2c interfaces:
|
||
i2c = new I2C
|
||
i2c.scl.line ~ <device>.<i2c scl pin>
|
||
i2c.sda.line ~ <device>.<i2c sda pin>
|
||
|
||
spi interfaces:
|
||
spi = new SPI
|
||
spi.sclk.line ~ <device>.<spi sclk pin>
|
||
spi.mosi.line ~ <device>.<spi mosi pin>
|
||
spi.miso.line ~ <device>.<spi miso pin>
|
||
|
||
8. Add decoupling capacitors
|
||
|
||
looking at the datasheet, determine the required decoupling capacitors
|
||
|
||
eg: 2x 100nF 0402:
|
||
|
||
power_3v3 = new ElectricPower
|
||
|
||
# Decoupling power_3v3
|
||
|
||
power_3v3_caps = new Capacitor[2]
|
||
for capacitor in power_3v3_caps:
|
||
capacitor.capacitance = 100nF +/- 20%
|
||
capacitor.package = "0402"
|
||
power_3v3.hv ~> capacitor ~> power_3v3.lv
|
||
|
||
9. If device has pin configurable i2c addresses
|
||
|
||
If format is: <n x fixed address bits><m x pin configured address bits>
|
||
use addressor module:
|
||
|
||
- Use `Addressor<address_bits=N>` where **N = number of address pins**.
|
||
- Connect each `address_lines[i].line` to the corresponding pin, and its `.reference` to a local power rail.
|
||
- Set `addressor.base` to the lowest possible address and `assert addressor.address is i2c.address`.
|
||
|
||
10. Create a README.md
|
||
|
||
# <Manufacturer> <Manufacturer part number> <Short description>
|
||
|
||
## Usage
|
||
|
||
```ato
|
||
<copy in example>
|
||
|
||
```
|
||
|
||
## Contributing
|
||
|
||
Contributions to this package are welcome via pull requests on the GitHub repository.
|
||
|
||
## License
|
||
|
||
This atopile package is provided under the [MIT License](https://opensource.org/license/mit/).
|
||
|
||
11. Connect high level interfaces directly in example:
|
||
|
||
eg:
|
||
|
||
i2c = new I2C
|
||
power = new ElectricPower
|
||
sensor = new Sensor
|
||
|
||
i2c ~ sensor.i2c
|
||
power ~ sensor.power_3v3
|
||
|
||
# Additional Notes & Gotchas (generic)
|
||
|
||
- Multi-rail devices (VDD / VDDIO, AVDD / DVDD, etc.)
|
||
|
||
- Model separate `ElectricPower` interfaces for each rail (e.g. `power_core`, `power_io`).
|
||
- Mark each `.required = True` if the device cannot function without it, and add voltage assertions per datasheet.
|
||
|
||
- Optional interfaces (SPI vs I²C)
|
||
|
||
- If the device supports multiple buses, pick one for the initial driver. Leave unused bus pins as `ElectricLogic` lines or expose a second interface module later.
|
||
|
||
- Decoupling guidance
|
||
|
||
- If the datasheet shows multiple caps, model the **minimum required** set so the build passes; you can refine values/packages later.
|
||
|
||
- File / directory layout recap
|
||
- `<vendor>-<device>/` – package root
|
||
- `ato.yaml` – build manifest (include `default` **and** `example` targets)
|
||
- `<device>.ato` – driver + optional example module
|
||
- `parts/<MANUFACTURER_PARTNO>/` – atomic part + footprint/symbol/step files
|
||
|
||
These tips should prevent common "footprint not found", "pin X missing", and build-time path errors when you add new devices.
|
||
|
||
|
||
# Vibe coding a project
|
||
|
||
If the user gives you high level description of the project, use the following guide:
|
||
|
||
# How LLMs can design electronics:
|
||
|
||
#1 Rule: USE THE TOOLS. If the tools dont work, dont freak out, you are probably using them wrong. Ask for help if you get stuck.
|
||
|
||
Top level design
|
||
|
||
1. Research available packages relevant to the user requests using 'find_packages'
|
||
2. Inspect promising packages using 'inspect_package'
|
||
3. Propose packages to use for project and architucture to user, revise if needed
|
||
4. Install needed packages using 'install_package'
|
||
5. Import packages into main file
|
||
6. Create instances of packages in main module
|
||
|
||
## Power
|
||
|
||
1. Review for each package the required voltage and current (current may not be provided, use judement if nessesary)
|
||
2. Determine the power rails that need to be generated and a suitable tollerance (typically ~3-5% is acceptable)
|
||
3. Determine the input power source, typically a battery, USB connector or other power connector (eg XT30) and install relevant package
|
||
4. Find suitable regulators:
|
||
a) if input voltage > required voltage and current is low, use an LDO package
|
||
b) if input voltage > required voltage and current is high, use buck converter
|
||
c) if input votlage < required voltage, use a boost converter
|
||
d) if input voltage can be both less than or greater than input voltage, use buck boost (eg battery powered device that needs 3v3)
|
||
5. If battery powered, add charger package
|
||
|
||
Typical power architucture example with LDO:
|
||
|
||
- USB input power
|
||
- Low current output (eg microcontroller)
|
||
|
||
from "atopile/ti-tlv75901/ti-tlv75901.ato" import TLV75901_driver
|
||
from "atopile/usb-connectors/usb-connectors.ato" import USBCConn
|
||
|
||
module App:
|
||
|
||
# Rails
|
||
power_5v = new Power
|
||
power_3v3 = new Power
|
||
|
||
# Components
|
||
ldo = new TLV75901_driver
|
||
usb_connector = new USBCConn
|
||
|
||
# Connections
|
||
usb_connector.power ~ power_vbus
|
||
power_vbus ~> ldo ~> power_3v3
|
||
|
||
## Communicaions
|
||
|
||
1. Review packages required interfaces, typically i2c, spi or ElectricLogics
|
||
2. Find suitable pins on the controller, typically a microcontroller or Linux SOC
|
||
3. Connect interfaces eg micro.i2c[0] ~ sensor.i2c
|
||
|
||
## Development process notes
|
||
|
||
- After making changes, be sure to use 'build_project' to update the PCB
|
||
- Builds will often generate errors/warnings, these should be reviewed and fixed
|
||
- Prioritize pacakges from 'atopile' over other packages
|
||
|
||
|